Recently, the utilization of asynchronous transfer mode, or ATM, technology with wide area networks, or WANs, has become increasingly popular. However, the use of ATM in wireless and satellite dependent networks has been limited, primarily due to noise considerations. ATM was originally designed for use in an optical fiber environment with bit-error-rates (BER) of 10.sup.-11 or less. As the BER increases to approximately 10.sup.-2, which is likely in radio applications including wireless and satellite applications, uncorrectable errors in the ATM cell header (i.e. errors greater than 1 bit) can prevent reliable delivery of the ATM cells.
A typical ATM packet, or cell, is shown in FIG. 1A. As seen in FIG. 1A, an ATM cell 100 includes a header portion 102 and a payload portion 104. Header portion 102 includes 5 bytes 106, 108, 110, 112 and 114 that contain routing and control information, while payload portion 104 includes 48 bytes of user data. Virtual circuits in an ATM link are identified by a header address contained within header portion 102. This header address may be 24 or 28 bits depending on whether the link is a user-network interface (UNI) or network-network interface (NNI), respectively. FIG. 1B shows header portion 102 in more detail, including the 5 bytes 106, 108, 110, 112 and 114 that make up header portion 102. In an NNI, the header address 120 includes the first 28 bits of header portion 102, while in a UNI, the header address includes 24 bits 122 as shown in FIG. 1B.
A conventional ATM cell switching method is described in connection with FIG. 2. It is important to note that in the conventional switching method a particular ATM header address, such as header address 120 or 122 shown in FIG. 1B, is only valid for a given link. For example, referring to FIG. 2, a cell sent by user 210 is transferred through two ATM switches 212 and 214 to an ATM network shown generally at 216. As the cell traverses through links 218, 220 and 222, it may have three different header addresses--one for each link. As long as each switch 212 and 214 recognizes the input address of the incoming cell, and routes it to the appropriate output port with an address recognizable by the next switch, the cell will eventually get to the correct destination.
Most ATM switches, such as switches 212 and 214 shown in FIG. 2, perform cell switching based on a connection table contained within the switch. For each input port that receives an ATM cell, its address is matched to a corresponding entry in the connection table that contains a corresponding output port number and output address. That is, a connection table for each input port on the switch contains a series of addresses that are matched to each of the incoming ATM cell's header addresses. A corresponding entry in the table contains an output port and output address. The output address is inserted into the ATM header, and the ATM cell is then output from the output port of the ATM switch. Thus, to provide full 28 bit addressing capability for an NNI link, the table must have 2.sup.28 entries. Most switches, however, use smaller connection tables.
FIG. 3 schematically illustrates such a connection table 300. Connection table 300 includes a section for each input port of the ATM switch. For example, a first section 310 corresponds to a first input port of the ATM switch; a second section 320 corresponds to a second input port; a third section 330 corresponds to a third input port; and so on to a section 340 corresponding to any arbitrary input port contained within the ATM switch. For each input port, a plurality of input addresses 312 are stored within connection table 300. For each input address 312, a corresponding output port and output address 314 are also stored within connection table 300. Thus, for the first section 310 corresponding to a first input port of the ATM switch, multiple input addresses 312, each having a corresponding output port and address 314, are stored within connection table 300. Thus, in operation, the ATM switch compares the input address of an incoming ATM cell to the portion of the connection table 300 corresponding to the input port on which the cell was received. When a matching input address is found, the ATM switch then routes the cell to the output port and address listed in connection table 300 that corresponds to the matching input address.
From the above, it will be apparent that bit errors occurring during transmission of an ATM cell can occur in either a header portion 102, a payload portion 104 or in both sections. When such errors occur in header portion 102 and more particularly in the header address 120 or 122, the ATM cell will likely not be routed to the correct destination. Specifically, if header address 120 or 122 of an ATM cell experience one or more uncorrected bit errors, then an ATM switch receiving the ATM cell will not find a match between the incoming header address and the input addresses stored within the connection table of the ATM switch. Thus, the switch will not be able to correctly route the ATM cell to the proper output port and address. Thus, the ATM cell will not reach its desired destination.
The often utilized method of applying bandwidth-costly forward-error-correction, or FEC, techniques to protect against such bit errors has serious drawbacks. One of the most serious drawbacks results because the use of FEC generally provides for error correction for an entire ATM link, including noise tolerant traffic, such as voice, that does not need to be protected from errors to the same degree as noise intolerant traffic, such as digital data, thus wasting precious bandwidth. A preferred solution then, must permit FEC (or realize the benefits from FEC) on a per virtual circuit basis. In other words, FEC should be applied only to selected noise sensitive traffic in a given link. Since virtual circuits in an ATM link are identified by the header address 120 or 122, an error tolerant addressing scheme is required to (a) identify the specific cells that require FEC, and (b) to correctly route those cells through a noisy link. Moreover, even voice traffic, where the payload portion 104 does not require FEC, will need some protection of the ATM cell header information in order to reduce misrouting of the cells.